The present invention relates generally to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having planar transistors with a fin-shaped channel region.
Integrated circuits (ICs), such as, ultra-large-scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed above a channel region and between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-inducted barrier-lowering. Shallow source and drain extensions, and hence controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region just below the top surface of the substrate to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. With the silicon dioxide spacers in place, the substrate is doped a second time to form deep source and drain regions. During formation of the deep source and drain regions, further doping of the source and drain extensions is inhibited due to the blocking characteristic of the silicon dioxide spacers. The deep source and drain regions are necessary to provide sufficient material to connect contacts to the source and drain regions.
As transistors become smaller, it is desirous to increase the charge carrier mobility in the channel region. Increasing charge carrier mobility increases the switching speed of the transistor. Channel regions formed from materials other than silicon have been proposed to increase charge carrier mobility. For example, conventional thin film transistors which typically utilize polysilicon channel regions have been formed on a silicon germanium (Sixe2x80x94Ge) epitaxial layer above a glass (SiO2) substrate. The Sixe2x80x94Ge epitaxial layer can be formed by a technique in which a semiconductor thin film, such as, an amorphous silicon hydride (a-Si:H), an amorphous germanium hydride (a-Ge:H) or the like is melted and crystallized by the irradiation of pulse laser beams.
In a bulk type device, such as, a metal oxide semiconductor field effect transistor (MOSFET), the use of Sixe2x80x94Ge materials could be used to increase charge carrier mobility, especially hole-type carriers. A tensile strained silicon channel region, such as, a silicon channel containing germanium, can have carrier mobility 2-5 times greater than a conventional Si channel region due to reduced carrier scattering and due to the reduced mass of holes in the germanium-containing material. According to conventional Sixe2x80x94Ge formation techniques for bulk-type devices, a dopant implant molecular beam epitaxy (MBE) technique forms a Sixe2x80x94Ge epitaxial layer. However, the MBE technique requires very complicated, very expensive equipment and is not feasible for mass production of ICs.
Double gate transistors, such as, double gate silicon-on-insulator (SOI) transistors have significant advantages related to high drive current and high immunity to short channel effects. An article by Huang, et al. entitled xe2x80x9cSub-50 nm FinFET: PMOSxe2x80x9d, (1999 IEDM) discusses a silicon transistor in which the active layer is surrounded by a gate on two sides. However, double gate structures can be difficult to manufacture using conventional IC fabrication tools and techniques. Further, patterning can be difficult because of the topography of silicon fin. At small critical dimensions, patterning may be impossible.
By way of example, a fin structure can be located over a layer of silicon dioxide. The fin structure can have located above it several different layers, including a photoresist layer, a bottom anti-reflective coating (BARC) layer, and a polysilicon layer. Various problems can exist with such a configuration. The photoresist layer may be thinner over the fin structure. In contrast, the polysilicon layer may be very thick at the edge of the fin structure. The BARC may be thick at the edge of the fin structure. Such a configuration leads to large over etch requirements for the BARC layer and the polysilicon layer. Such requirements increase the size of the transistor.
Thus, there is a need for an integrated circuit or electronic device that includes channel regions with higher channel mobility, higher immunity to short channel effects and higher drive current. Further, there is a need for patterning finFET devices having small critical dimensions. Even further, there is a need for using amorphous carbon in patterning finFET devices.
An exemplary embodiment relates to a method of finFET patterning. The method can include patterning a fin structure above a substrate, forming amorphous carbon spacers along lateral sidewalls of the fin structure, depositing an oxide layer and polishing the oxide layer to expose top portions of the fin structure and the amorphous carbon spacers, removing amorphous carbon spacers, and depositing polysilicon where the amorphous carbon spacers were located.
Another exemplary embodiment relates to a method of finFET gate patterning. The method can include providing amorphous carbon spacers adjacent a fin structure, providing a layer of oxide adjacent the amorphous carbon spacers, removing the amorphous carbon spacers, and forming a gate structure above the fin structure and where the amorphous carbon spacers were located.
Another exemplary embodiment relates to a patterning method. The method can include forming a fin structure having a silicon portion and silicon dioxide portion, forming spacers adjacent lateral sidewalls of the fin structure, forming a layer adjacent to and co-planar with the spacers, removing the spacers, and depositing polysilicon where the spacers were located. The fin structure has a critical dimension of 10-50 nm. The spacers include amorphous carbon.